//指令:0x44	         0x01	        0x07	        0x00	        0x00	        0x00	        0x00	        0x00
//含义:包头     cmd_inde[15:8]   cmd_inde[7:0]  par_index[31:24] par_index[23:16] par_index[15:8] par_index[7:0]     包尾
//包头固定为0x44 包尾固定为0x00
module uart_cmd_top#(
parameter  CLK_FREQ  = 50_000_000,
parameter  BAUD_RATE = 921600   ,
parameter  PLATFORM  = 0         //0:Altera 1:Xilinx 2:GoWin 3:Anlogic

)(
    input          clk     ,
    input          rst_n   ,
    input          uart_rxd,
    output         uart_txd,
    //发送指令
    input          tx_cmd_valid ,
    input [15:0]   tx_cmd_index ,//指令
    input [31:0]   tx_par_index ,//参数
    //接收指令
    output         rx_cmd_valid ,
    output [15:0]  rx_cmd_index ,//指令
    output [31:0]  rx_par_index  //参数
);
wire [7:0] tx_data,rx_data;
wire       tx_en;
wire       rd_empty,rd_en;
reg        rx_en;
assign rd_en = ~rd_empty;
always@(posedge clk or negedge rst_n)
if(~rst_n) rx_en <= 1'b0;
else       rx_en <= rd_en;
cmd_dec u_cmd_dec_0(
    .clk       (clk    ),
	.rst_n     (rst_n  ),
	.data      (rx_data),
	.data_valid(rx_en  ),
	.cmd_valid (rx_cmd_valid),
	.cmd_index (rx_cmd_index),//指令
	.par_index (rx_par_index) //参数
);
fifo_port_uart #(
	.CLK_FREQ (CLK_FREQ ),
	.BAUD_RATE(BAUD_RATE),
	.PLATFORM (PLATFORM )  //0:Altera 1:Xilinx 2:GoWin 3:Anlogic

)u_fifo_port_uart_0(
    .clk50M  (clk    ),
	.rst_n   (rst_n  ),
	.data    (tx_data),
	.write   (tx_en  ),
	.wr_full (),
	.rd_empty(rd_empty),
	.read    (rd_en   ),
	.q       (rx_data ),
	.uart_rxd(uart_rxd),
	.uart_txd(uart_txd)
);
cmd_enc u_cmd_enc_0(
    .clk       (clk         ),
	.rst_n     (rst_n       ),
	.data      (tx_data     ),
	.data_valid(tx_en       ),
	.cmd_valid (tx_cmd_valid),
	.cmd_index (tx_cmd_index),//指令
	.par_index (tx_par_index)//参数

);
endmodule 